1. Field of the Invention
The invention relates to the process of designing and fabricating semiconductor chips. More specifically, the invention relates to a method and an apparatus for selectively varying how much of a layout is defined by phase shifters during an optical lithography process for manufacturing an integrated circuit.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. As the feature size of these circuit elements continues to decrease, circuit designers are forced to deal with problems that arise during the optical lithography processes that are used to manufacture integrated circuits. This optical lithography process generally begins with the formation of a photoresist layer on the surface of a semiconductor wafer. A mask composed of opaque regions, which are generally formed of chrome, and light-transmissive clear regions, which are generally formed of quartz, is then positioned over this photo resist layer coated wafer. (Note that the term xe2x80x9cmaskxe2x80x9d as used in this specification is meant to include the term xe2x80x9creticle.xe2x80x9d) Light is then shone on the mask from a visible light source or an ultraviolet light source.
This light is generally reduced and focused through an optical system that contains a number of lenses, filters and mirrors. The light passes through the clear regions of the mask and exposes the underlying photoresist layer. At the same time, the light is blocked by opaque regions of mask, leaving underlying portions of the photoresist layer unexposed.
The exposed photoresist layer is then developed, typically through chemical removal of the exposed/non-exposed regions of the photoresist layer. The end result is a semiconductor wafer with a photoresist layer having a desired pattern. This pattern can then be used for etching/implanting on underlying regions of the wafer.
Phase shifters are often incorporated into a mask in order to achieve line widths that are smaller than the wavelength of the light that is used to expose the photoresist layer through the mask. During phase shifting, destructive interference caused by two adjacent clear areas on a mask is used to create an unexposed area on the photoresist layer. This is accomplished by exploiting the fact that light passing through a mask""s clear regions exhibits a wave characteristic having a phase that is a function of the distance the light travels through the mask material. By placing two clear areas adjacent to each other on the mask, one of thickness t1 and the other of thickness t2, one can obtain a desired unexposed area on the underlying photoresist layer caused by interference. By varying the thickness t1 and t2 appropriately, the light exiting the material of thickness t2 is 180 degrees out of phase with the light exiting the material of thickness to. Phase shifting is described in more detail in U.S. Pat. No. 5,858,580, entitled xe2x80x9cPhase Shifting Circuit Manufacture Method and Apparatus,xe2x80x9d by inventors Yao-Ting Wang and Yagyensh C. Pati, filed Sep. 17, 1997 and issued Jan. 12, 1999.
For example, FIG. 1 illustrates how a phase shifter comprised of a zero-degree clear region 104 and a 180-degree clear region 106 is used to achieve a smaller line width for a gate region of a transistor. As circuit dimensions on semiconductor chips become progressively smaller, phase shifters are presently being used to define other critical-dimension features in addition to transistor gates. FIG. 2 illustrates how phase shifters are additionally used to define interconnections between phase shifters. For example, in FIG. 2 phase shifters 210-213 are used to define the gates of four different transistors 202-205 in the circuit layout. However, phase shifters 210-212 additionally extend past these gate regions to additionally define interconnections between the gates. Note that in FIG. 2, phase shifters are represented by diagonal lines, non-phase-shifted features are represented by cross-hatching, phase-shifted regions are clear and diffusion regions are represented by a grid pattern.
Note that FIG. 1 and FIG. 2 do not show masks, but rather a composite layout showing the resultant design and the phase shift areas. In order to produce these features, two masks are generally used: one dark field mask with the phase shifters; and the other a complementary trim mask with protection for regions defined by the phase shifting mask and to define cross-hatched areas.
Phase shifting is used to define the gate regions of transistors. However, as feature sizes continue to decrease, it is becoming increasingly desirable to use phase shifters to define other features of an integrated circuit.
Unfortunately, as phase shifters are used define more critical dimension features, coloring conflicts are likely to arise between phase shifters. Phase shifters operate by creating interference patterns between zero-degree clear regions and 180-degree clear regions. Coloring conflicts arise when nearby phase shifting regions have the same phase. For example, when a first zero-degree clear region is in close proximity to a second zero-degree clear region, light from the first clear region reinforces light from the second clear region on the photoresist layer between the first and second clear regions. This can cause unwanted exposure of the photoresist layer.
In order to prevent this problem, systems that lay out, or design, phase shifting layouts typically perform tests to ensure that coloring conflicts do not occur. When a coloring conflict is detected, phase shifters are either removed or reduced in size through a manual process to mitigate the coloring conflict. This manual process can be extremely time-consuming, especially when large numbers of phase shifters are involved. Moreover, it is difficult to determine how much of a circuit layout can be phase shifted without creating coloring conflicts.
What is needed is a method and an apparatus that facilitates automatically performing phase shifting on as much of a circuit layout as is possible without creating coloring conflicts.
One embodiment of the invention provides a system that facilitates selectively varying how much of a layout of an integrated circuit is defined by phase shifters during an optical lithography process used in manufacturing the integrated circuit. During operation, the system receives a specification of the layout of the integrated circuit. The system then assigns features within the layout to zones associated with different phase shifting priorities. Next, the system generates a phase shifter placement by placing phase shifters comprised of phase shifting geometries onto a phase shifting mask to define the features within the layout, wherein the phase shifter placement is subject to coloring constraints. Note that in general there is no restriction on the order of zone placement. (For example, it is possible to place all zones first before verifying colorability.) During this placement process, if coloring constraints cannot be satisfied, the system resolves conflicts and/or removes features from being phase-shifted based upon phase shifting priorities of the zones.
In a variation on this embodiment, the system receives a phase shifting level from a user interface element, and uses this phase shifting level to determine which zones are subject to phase shifting based on a priority ordering, wherein zones of higher priority are phase shifted before zones of lower priority. This user interface element can include: a slider, a set of buttons, a pulldown menu, or an input field. In other embodiments, the input is provided from one or more data files.
In a variation on this embodiment, assigning the features to zones involves applying a set rules that specify how to assign features to zones. In a further variation, the system assigns features to zones based on at least one of: feature type (e.g., gates, interconnects, metal, etc.), feature dimension (e.g., feature width, feature length, etc.), specific feature interaction with layer (e.g., feature overlapping with specific layer in layout), and feature proximity to predefined features (e.g., interconnect within certain range from gate).
In a variation on this embodiment, while placing the phase shifters, the system uses a phase shifter width associated with a phase shifting zone.
In a variation on this embodiment, the system additionally performs a coloring operation to determine whether the phase shifter placement causes a phase shifter conflict. If a phase shifter conflict is detected, the system scales back the phase shifter placement to eliminate the phase shifter conflict. This process of scaling back the phase shifter placement can involve removing phase shifters from a zone of lowest priority that has been phase shifted so far, or changing placement parameters for one or more phase shifting zones.
In a variation on this embodiment, placing phase shifters involves iteratively placing phase shifters for zones starting with a zone of highest priority and proceeding in descending priority order to zones of lower priority until a coloring conflict is encountered.
In a variation on this embodiment, the system runs a test mask through the optical lithography process and/or a simulation of all or part of the process to produce test results, and uses the test results to generate a set of rules specifying how to assign features to zones. The system also uses the test results to generate phase shifter widths for the zones.